Semiconductor device, display device and method of fabricating the same

ABSTRACT

A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device such as athin film transistor (TFT), a method of fabricating the same, a displaydevice such as a liquid crystal display (LCD), and a method offabricating the same.

[0003] 2. Description of the Background Art

[0004] A thin film transistor (hereinafter referred to as apolycrystalline silicon TFT) employing a polycrystalline silicon filmwhich is formed on a transparent insulating substrate as an active layeris recently being developed as each pixel driving element (pixel drivingtransistor) for an active matrix LCD.

[0005] The polycrystalline silicon TFT advantageously has largermobility and higher drivability as compared with a thin film transistoremploying an amorphous silicon film as an active layer. When suchpolycrystalline silicon TFTs are employed, therefore, an LCD of highperformance LCD can be implemented while not only a pixel part (displaypart) but a peripheral driving circuit (driver part) can be integrallyformed on the same substrate.

[0006] In such a polycrystalline silicon TFT, the polycrystallinesilicon film for serving as an active layer can be formed by a method ofdirectly depositing the polycrystalline silicon film on the substrate, amethod of forming an amorphous silicon film on the substrate andthereafter polycrystallizing the same, or the like.

[0007] The method of directly depositing the polycrystalline siliconfilm on the substrate has a relatively simple step of depositing thefilm by CVD, for example, under a high temperature, for example.

[0008] On the other hand, the amorphous silicon film which is depositedon the substrate is thereafter polycrystallized by solid-phasecrystallization in general. This solid-phase crystallization is adaptedto polycrystallize the amorphous silicon film in a solid state byperforming a heat treatment, for obtaining the polycrystalline siliconfilm.

[0009] An example of such solid-phase crystallization is now describedwith reference to FIGS. 31 and 32.

[0010] Step A (see FIG. 31): An amorphous silicon film is formed on aninsulating substrate 51 of quartz glass, for example, by general lowpressure CVD, and a heat treatment is performed in a nitrogen (N₂)atmosphere at a temperature of about 900° C., thereby solid-phasegrowing the amorphous silicon film and forming a polycrystalline siliconfilm 52.

[0011] The polycrystalline silicon film 52 is worked into a prescribedshape by photolithography and dry etching by RIE, to be employed as anactive layer of a thin film transistor.

[0012] A silicon oxide film for serving as a gate insulating film 53 isdeposited on the polycrystalline silicon film 52 by low pressure CVD.

[0013] Step B (see FIG. 32): A polycrystalline silicon film is depositedon the gate insulating film 53 by low pressure CVD, an impurity isimplanted into this polycrystalline silicon film, and a heat treatmentis performed for activating the impurity.

[0014] Then, a silicon oxide film 54 is deposited on the polycrystallinesilicon film by normal pressure CVD, and thereafter the polycrystallinesilicon film and the silicon oxide film 54 are worked into prescribedshapes by photolithography and dry etching by RIE. The polycrystallinesilicon film is employed as a gate electrode 55.

[0015] Then, an impurity is implanted into the polycrystalline siliconfilm 52 by self alignment through the gate electrode 55 and the siliconoxide film 54 serving as masks, for forming source/drain regions 56.

[0016] This method is called a high temperature process since hightemperatures of about 900° C. are employed for the solid-phasecrystallization and the impurity activation, and has such an advantagethat the treatment time can be shortened when a substrate such as aquartz substrate, for example, having a high insulation property isemployed.

[0017] However, such a substrate having a high insulation property ishigh-priced, while a relatively low-priced glass substrate unpreferablycauses heat distortion. In recent years, therefore, development isgenerally made in a low temperature process which allows the employmentof the glass substrate.

[0018] In particular, improvement of performance is indispensable in aTFT which is a driving device. Therefore, various attempts have beenmade in order to improve the quality of the material forming the TFT andthe like through the low temperature process.

[0019] For example, a technique of forming a polycrystalline siliconthin film, for example, by excimer laser annealing with a startingmaterial of an amorphous silicon film has been developed as a techniqueof improving the quality of an active layer material influencing thedevice characteristics.

[0020] However, the laser annealing disadvantageously requires a longtime for the crystallization process, since a beam operation must berepeatedly performed. In case of employing only a laser beam as a heatsource, the laser annealing requiring a long time must also be performedfor activating an impurity region, for example, in addition to thepolycrystallization process, and hence the total process time isincreased to reduce the throughput of such a TFT device or an LCD deviceemploying the TFT.

SUMMARY OF THE INVENTION

[0021] An object of the present invention to enable a low temperatureprocess with employment of a low-priced substrate, for reducing the costfor fabricating a thin film transistor or a liquid crystal display.

[0022] Another object of the present invention is to improve thethroughput in fabrication of a thin film transistor or a liquid crystaldisplay by fabricating a high-quality polycrystalline silicon film in ashort time.

[0023] Still another object of the present invention is to fabricate asemiconductor device having excellent quality with a homogeneouslyactivated impurity region.

[0024] A further object of the present invention is to fabricate asemiconductor device having a high-quality semiconductor film in a shorttime.

[0025] A further object of the present invention is to provide a displaydevice such as an LCD device having excellent display performance.

[0026] A further object of the present invention is to preventdeformation of a substrate in a heat treatment.

[0027] A further object of the present invention is to prevent warp andbreakage of a substrate in case of employing RTA (rapid thermalannealing) as a heat treatment.

[0028] A method of fabricating a thin film transistor according to afirst aspect of the present invention is adapted to set the temperaturefor a heat treatment for crystallizing an active layer which is formedon a substrate is set at a level not deforming the substrate, forexample 600-700° C., for activating an impurity by a heat treatmentmethod which is different from that employed for this heat treatment.

[0029] According to the first aspect of the present invention,polycrystallization of an amorphous silicon film and activation of animpurity region can be performed by properly combining the heattreatment method employing a temperature not deforming the substrate,laser annealing and RTA with each other, whereby the fabrication time isshorted as compared with a method of performing both ofpolycrystallization and activation by laser annealing.

[0030] According to a preferred embodiment of the first aspect, themethod comprises the steps of forming an amorphous silicon film on aninsulating substrate, heat treating the amorphous silicon film by laserannealing or RTA (rapid thermal annealing) employing a temperature notdeforming the substrate thereby forming a polycrystalline silicon film,forming a gate electrode on the polycrystalline silicon film through agate insulating film, forming an impurity region in the polycrystallinesilicon film, and activating the impurity region by rapid heatingemploying RTA or laser annealing.

[0031] According to this method, a number of substrates can besimultaneously treated in solid-phase crystallization.

[0032] In the first aspect of the present invention, the amorphoussilicon film may contain microcrystals. When such an amorphous siliconfilm containing microcrystals is polycrystallized by solid-phasecrystallization, the crystal growth can be completed in a short time.

[0033] In the first aspect, the gate electrode may have at. least theamorphous silicon film, and may be crystallized by the heat treatmentfor activating the impurity. In this method, crystallization of theamorphous silicon film and activation of the impurity are performed atonce, whereby the treatment time is shortened as compared with a methodof performing these operations independently of each other.

[0034] In the first aspect, the gate electrode may have a two-layerstructure of at least a silicon film and a metal or metal silicide film,and may be reduced in resistance by the heat treatment for activatingthe impurity. According to this method, reduction of resistance of thetwo-layer structure of the silicon film and the metal or metal silicidefilm and activation of the impurity are performed at once, whereby thetreatment time is shorted as compared with the case of separatelyperforming these operations.

[0035] The gate electrode comprising the two-layer structure of asilicon film and a metal or metal silicide film may be provided so thatreduction in resistance of the gate electrode and activation of theimpurity region are simultaneously performed by RTA or laser annealing.

[0036] In the first aspect, light irradiation heat from a lamp may beemployed as a heat source for the RTA. This lamp may be formed by anxenon arc lamp. A heat treatment which is more suitable for activationof the impurity can be performed by employing such a lamp.

[0037] A thin film transistor fabricated by the method of fabricating athin film transistor according the first aspect of the present inventioncan be employed as each pixel driving element of a liquid crystaldisplay. Alternatively, the thin film transistor can be employed as eachperipheral driving circuit element of the liquid crystal display. Thus,an excellent liquid crystal display can be fabricated in a short time.

[0038] A semiconductor device according to a second aspect of thepresent invention comprises a heat absorption film which is formed on asubstrate, a semiconductor film which is formed on the heat absorptionfilm, a gate electrode which is formed on the semiconductor film througha gate insulating film, and an impurity region which is formed in thesemiconductor film, and the heat absorption film is provided within aregion substantially corresponding to the semiconductor film.

[0039] According to the second aspect, a semiconductor device having animpurity region of a homogeneously activated state can be obtained dueto the presence of the heat absorption film.

[0040] In the second aspect, an insulating film may be provided betweenthe heat absorption film and the semiconductor film.

[0041] In the second aspect, the heat absorption film may be provided ina size and within a region substantially corresponding to a channelregion in the semiconductor film. Thus, the function of the heatabsorption film properly acts on a necessary portion, so that no badinfluence is exerted on the remaining portion such as the substrate, forexample.

[0042] In the second aspect, the heat absorption film may be made of aconductive material such as a metal or metal silicide, or asemiconductor material such as silicon. Thus, the device can beelectrostatically shielded against ions which are present in thesubstrate since the heat absorption film is made of a conductive orsemiconductor material.

[0043] In the second aspect, the heat absorption film may have a shadingproperty. When the semiconductor device is employed for a display devicesuch as an LCD, the quantity of light directly entering thesemiconductor device can be reduced due to the shading property of theheat absorption film.

[0044] In the second aspect, the substrate may be a transparentsubstrate.

[0045] The semiconductor device according to the second aspect of thepresent invention can be employed as at least one of each pixel drivingelement or each peripheral driving circuit element of a liquid crystaldisplay. Thus, an excellent display device can be obtained.

[0046] A method of fabricating a semiconductor device according to athird aspect of the present invention is adapted to provide asemiconductor film for serving as an active layer of a transistor on asubstrate through a heat absorption film, and to activate an impurityregion provided in the semiconductor film by a heat treatment.

[0047] According to the fabrication method of the third aspect, asemiconductor device having an impurity region which is in anexcellently and homogeneously activated state can be obtained.

[0048] According to a preferred embodiment of the present invention, themethod comprises the steps of forming a heat absorption film on atransparent substrate, forming a semiconductor film on the heatabsorption film, forming a gate electrode on the semiconductor filmthrough a gate insulating film, forming an impurity region in thesemiconductor film, and activating the impurity region by a heattreatment, and the heat absorption film being provided within a regionsubstantially corresponding to the semiconductor film.

[0049] According to another preferred embodiment of the presentinvention, the method comprises the steps of forming a heat absorptionfilm on a transparent substrate, working the heat absorption film into aprescribed shape, covering the heat absorption film with an insulatingfilm, forming a semiconductor film for serving as an active layer of atransistor on the insulating film, forming a gate electrode on thesemiconductor film through a gate insulating film, forming an impurityregion in the semiconductor film, and activating the impurity region bya heat treatment, and the heat absorption film being provided within aregion substantially corresponding to the semiconductor film.

[0050] In the third aspect, the semiconductor film may be prepared bypolycrystallizing an amorphous silicon film by a heat treatment.

[0051] In the third aspect, the heat treatment may be performed by laserannealing.

[0052] In the third aspect, the heat absorption film may be made of aconductive material such as a metal or metal silicide, or asemiconductor material such as silicon. The device can beelectrostatically shielded against ions which are present in thesubstrate by preparing the heat absorption film from a conductive orsemiconductor material.

[0053] The heat absorption film may have a shading property. Thus, thequantity of light directly entering the semiconductor device can bereduced when the semiconductor device is applied to a display devicesuch as an LCD.

[0054] RTA may be employed as the heat treatment. In this case, theimpurity can be activated in a short time without influencing thesubstrate.

[0055] The heat source for RTA can be formed by a xenon arc lamp. Inthis case, heat absorption can be efficiently performed.

[0056] A semiconductor device fabricated by the method according to thethird aspect of the present invention can be employed as at least one ofeach pixel driving element and each peripheral driving circuit elementof a liquid crystal display. Thus, an excellent display device can befabricated in a short time.

[0057] A semiconductor device according to a fourth aspect of thepresent invention comprises a plurality of semiconductor elements whichare integrated on a substrate. Heat absorption films are providedbetween the substrate and the semiconductor elements, and an area orfilm thickness of each heat absorption film is relatively reduced in aportion where a relatively large number of the semiconductor elementsare provided, while an area or film thickness of each heat absorptionfilm is relatively increased in a portion where a relatively smallnumber of the semiconductor elements are provided, in accordance withthe distributed state of the semiconductor elements on the substrate.

[0058] According to a preferred embodiment of the fourth aspect, aplurality of semiconductor switching elements are integrated on asubstrate, and each semiconductor switching element comprises a heatabsorption film which is formed on the substrate, a semiconductor filmwhich is formed on the heat absorption film, a gate electrode which isformed on the semiconductor film through a gate insulating film, and animpurity region which is formed in the semiconductor film. An area orfilm thickness of each heat absorption film is relatively reduced in aportion where a relatively large number of the semiconductor switchingelements are provided, while an area or film thickness of each heatabsorption film is relatively increased in a portion where a relativelysmall number of the semiconductor switching elements are provided, inaccordance with the distributed state of the semiconductor switchingelements on the substrate.

[0059] In the fourth aspect, the heat absorption effects of the heatabsorption films can be adjusted by changing the areas and/or thethicknesses of the heat absorption films.

[0060] In the fourth aspect, the heat absorption effects of the heatabsorption films can be adjusted by providing semiconductor switchingelements having no heat absorption films and changing the ratio ofpresence of such semiconductor switching elements.

[0061] Each of the heat absorption films in the fourth aspect can beprepared from a film which is similar to those according to the secondand third aspects.

[0062] A display device according to the fourth aspect of the presentinvention is a driver-integrated display device comprising a pixel partand a peripheral driving circuit part which are formed on the samesubstrate. This display device comprises pixel driving elements whichare provided in the pixel part and peripheral driving circuit elementswhich are provided in the peripheral driving circuit part, and the pixeldriving elements and the peripheral driving circuit elements are formedby semiconductor switching elements. Each semiconductor switchingelement comprises a heat absorption film which is formed on thesubstrate, a semiconductor film which is formed on the heat absorptionfilm, a gate electrode which is formed on the semiconductor film througha gate insulating film, and an impurity region which is formed on thesemiconductor film. A ratio of area or film thickness of the heatabsorption film relative to the semiconductor film in the pixel part isadjusted to be larger than that of the heat absorption film in theperipheral driving circuit part.

[0063] The pixel part and the peripheral driving circuit part can beprovided on one of a pair of substrates which are opposed to each otherthrough a liquid crystal layer. Each of the heat absorption films can beformed by a film which is similar to those of the second and thirdaspects.

[0064] The heat absorption effects of the heat absorption films can beadjusted by changing the areas or thicknesses of the heat absorptionfilms.

[0065] Alternatively, the heat absorption effects of the heat absorptionfilms can be adjusted by providing semiconductor switching elementshaving no heat absorption films and changing the ratio of presence ofthese semiconductor switching elements.

[0066] A method of fabricating a semiconductor device according to afifth aspect of the present invention employs RTA for a heat treatmentin a process of forming a semiconductor element on a substrate, andheating by RTA is performed in a plurality of times, while the heatingtemperature is increased stepwise from the initial time toward the finaltime.

[0067] According to a preferred embodiment of the fifth aspect, thefabrication method comprises the steps of forming a semiconductor filmon a substrate, forming a gate electrode on the semiconductor filmthrough a gate insulating film, forming an impurity region in thesemiconductor film, and activating the impurity region by a heattreatment through RTA, while heating by RTA is performed a plurality oftimes and the heating temperature is increased stepwise from the initialtime toward the final time.

[0068] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0069]FIG. 1 is a sectional view for illustrating a fabrication step ina first embodiment according to the first aspect of the presentinvention;

[0070]FIG. 2 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0071]FIG. 3 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0072]FIG. 4 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0073]FIG. 5 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0074]FIG. 6 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0075]FIG. 7 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0076]FIG. 8 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0077]FIG. 9 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0078]FIG. 10 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0079]FIG. 11 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0080]FIG. 12 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0081]FIG. 13 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0082]FIG. 14 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0083]FIG. 15 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0084]FIG. 16 is a sectional view for illustrating a fabrication step inthe first embodiment according to the first aspect of the presentinvention;

[0085]FIG. 17 is a block diagram showing an active matrix LCD;

[0086]FIG. 18 is an equivalent circuit diagram of a pixel part;

[0087]FIG. 19 is a sectional view for illustrating a fabrication step ina second embodiment according to the first aspect of the presentinvention;

[0088]FIG. 20 is a sectional view for illustrating a fabrication step inthe second embodiment according to the first aspect of the presentinvention;

[0089]FIG. 21 is a sectional view for illustrating a fabrication step inthe second embodiment according to the first aspect of the presentinvention;

[0090]FIG. 22 is a sectional view for illustrating a fabrication step inthe second embodiment according to the first aspect of the presentinvention;

[0091]FIG. 23 is a sectional view for illustrating a fabrication step inthe second embodiment according to the first aspect of the presentinvention;

[0092]FIG. 24 is a sectional view for illustrating a fabrication step inthe second embodiment according to the first aspect of the presentinvention;

[0093]FIG. 25 is a sectional view for illustrating a fabrication step inthe second embodiment according to the first aspect of the presentinvention;

[0094]FIG. 26 is a sectional view for illustrating a fabrication step inthe second embodiment according to the first aspect of the presentinvention;

[0095]FIG. 27 is a sectional view for illustrating a fabrication step inthe second embodiment according to the first aspect of the presentinvention;

[0096]FIG. 28 is a sectional view for illustrating a fabrication step inthe second embodiment according to the first aspect of the presentinvention;

[0097]FIG. 29 is a block diagram showing an excimer laser annealingdevice;

[0098]FIG. 30 is a block diagram of an RTA device;

[0099]FIG. 31 is a sectional view showing an exemplary conventionalfabrication step;

[0100]FIG. 32 is a sectional view showing an exemplary conventionalfabrication step;

[0101]FIG. 33 is a sectional view for illustrating a fabrication step inan embodiment according to the second to fifth aspects of the presentinvention;

[0102]FIG. 34 is a sectional view for illustrating a fabrication step inthe embodiment according to the second to fifth aspects of the presentinvention;

[0103]FIG. 35 is a sectional view for illustrating a fabrication step inthe embodiment according to the second to fifth aspects of the presentinvention;

[0104]FIG. 36 is a sectional view for illustrating a fabrication step inthe embodiment according to the second to fifth aspects of the presentinvention;

[0105]FIG. 37 is a sectional view for illustrating a fabrication step inthe embodiment according to the second to fifth aspects of the presentinvention;

[0106]FIG. 38 is a sectional view for illustrating a fabrication step inthe embodiment according to the second to fifth aspects of the presentinvention;

[0107]FIG. 39 is a sectional view for illustrating a fabrication step inthe embodiment according to the second to fifth aspects of the presentinvention;

[0108]FIG. 40 is a sectional view for illustrating a fabrication step inthe embodiment according to the second to fifth aspects of the presentinvention;

[0109]FIG. 41 is a sectional view for illustrating a fabrication step inthe embodiment according to the second to fifth aspects of the presentinvention;

[0110]FIG. 42 is a sectional view for illustrating a fabrication step inthe embodiment according to the second to fifth aspects of the presentinvention; and

[0111]FIG. 43 is a sectional view showing the structure of a pixel partof an LCD according to an embodiment of the present invention.

[0112]FIG. 44 is a plan view showing an exemplary region for forming aheat absorption film according to the present invention.

[0113]FIG. 45 is a plan view showing another exemplary region forforming a heat absorption film according to the present invention.

[0114]FIG. 46 is a plan view for describing ratios of heat absorptionfilms in a pixel part, a peripheral driving circuit part, and the otherregion on a substrate.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0115] A first embodiment according to the first aspect of the presentinvention is now described with reference to FIGS. 1 to 18.

[0116] Step 1 (see FIG. 1): An insulating thin film 1 a of SiO₂ or SiNis formed on a substrate 1 of quartz glass or no-alkali glass by CVD orsputtering. In the concrete, the substrate 1 is prepared from 7059 byCorning Inc., and an SiO₂ film of 3000 to 5000 Å in thickness is formedon its surface at a formation temperature of 350° C. by normal or lowpressure CVD.

[0117] This SiO₂ film must have such a thickness that no impurity passesthrough the SiO₂ film to diffuse into an upper layer from the substrate1 in a later step of a heat treatment or irradiation with a beam. Thisthickness is properly selected in the range of 1000 to 6000 Å, and anexcellent diffusion preventing effect can be attained when the thicknessis in the range of 2000 to 6000 Å, most properly in the range of 2000 to3000 Å.

[0118] When the insulating thin film la is prepared from SiN, on theother hand, the thickness of this film is properly selected in the rangeof 1000 to 5000 Å, and an excellent diffusion preventing effect can beattained when the thickness is in the range of 2000 to 5000 Å, mostproperly in the range of 2000 to 3000 Å.

[0119] Step 2 (see FIG. 2): An amorphous silicon film 2 a of 500 Å inthickness is formed on the insulating thin film 1 a. When the amorphoussilicon film 2 a is employed as an active layer of a polycrystallineTFT, the OFF-state current of the TFT is increased if the thickness ofthe active layer is too large while the ON-state current is reduced ifthe thickness is too small. Therefore, the thickness of the amorphoussilicon film 2 a is properly selected in the range of 400 to 800 Å, andexcellent characteristics are attained when the thickness is in therange of 500 to 700 Å, most properly in the range of 500 to 600 Å.

[0120] The amorphous silicon film 2 a is formed in the following manner:

[0121] (1) With employment of low pressure CVD: In order to form theamorphous silicon film 2 a by low pressure CVD, thermal decomposition ofmonosilane (SiH₄) or disilane (Si₂H₆) is employed. When monosilane isemployed, the film becomes amorphous when the treatment temperature isnot more than 550° C., or becomes polycrystalline when the treatmenttemperature is in excess of 620° C. In the treatment temperature rangeof 550 to 620° C., the ratio of amorphous materials includingmicrocrystals is increased, while the film approaches an amorphous stateand the ratio of the microcrystals is reduced as the temperature isreduced. Thus, the amount of microcrystals contained in the amorphoussilicon film 2 a can be adjusted by simply changing the temperaturecondition.

[0122] (2) With employment of plasma CVD: In order to form the amorphoussilicon film 2 a by plasma CVD, thermal decomposition of monosilane ordisilane in a plasma is employed.

[0123] In practice, plasma CVD is employed for forming an amorphoussilicon film containing no microcrystals with employment of monosilanegas under a temperature of 350° C.

[0124] Step 3 (see FIG. 3): The surface of the amorphous silicon film 2a is irradiated and scanned with a KrF excimer laser beam having awavelength λ of 248 nm to be annealed, melted and recrystallized forforming a polycrystalline silicon thin film 2.

[0125] The laser conditions for this step are an annealing atmosphere ofnot more than 1×10⁻⁴ Pa, a substrate temperature in the range of theroom temperature to 600° C., irradiation energy density of 100 to 500mJ/cm², and a scanning rate of 1 to 10 mm/sec. (in practice, the filmcan be scanned at a rate in the range of 0.1 to 100 mm/sec.).

[0126] The KrF laser beam may be replaced with an XeCl excimer laserbeam having a wavelength λ of 308 nm. In this case, the laser conditionsare an annealing atmosphere of not more than 1×10⁻⁴ Pa, a substratetemperature in the range of the room temperature to 600° C., irradiationenergy density of 100 to 500 mJ/cm², and a scanning rate of 1 to 10mm/sec. (in practice, the film can be scanned at a rate in the range of0.1 to 100 mm/sec.).

[0127] Alternatively, an ArF excimer laser beam having a wavelength λ of193 nm may be employed. In this case, the laser conditions are anannealing atmosphere of not more than 1×10⁻⁴ Pa, a substrate temperaturein the range of the room temperature to 600° C., irradiation energydensity of 100 to 500 mJ/cm², and a scanning rate of 1 to 10 mm/sec.

[0128] In any case, the grain size of polycrystalline silicon isincreased in proportion to the irradiation energy density and the numberof irradiation times, and hence the energy density and the number ofirradiation times may be adjusted to attain a desired grain size.

[0129] According to this embodiment, high throughput laser irradiationis employed for the excimer laser annealing. Referring to FIG. 29,numeral 101 denotes a KrF excimer laser unit, numeral 102 denotes areflecting mirror for reflecting a laser beam from the laser unit 101,and numeral 103 denotes a laser beam control optical system for workingthe laser beam received from the reflecting mirror 102 into a prescribedstate and applying the same to a substrate 1.

[0130] In such a structure, the high throughput laser irradiation isadapted to apply the laser beam which is worked in the form of a sheetof 150 mm by 0.5 mm by the laser beam control optical system 103 bysuperposing a plurality of pulses with each other, for completelysynchronizing stage scanning with pulse laser irradiation andirradiating the substrate with the laser beam in superposition ofextremely high accuracy, thereby improving the throughput.

[0131] Step 4 (see FIG. 4): The polycrystalline silicon film 2 is workedinto a prescribed shape by photolithography and dry etching by RIE, tobe employed as an active layer of a thin film transistor.

[0132] Then, an LTO film (low temperature oxide film: silicon oxidefilm) 3 of 1000 Å in thickness for serving as a gate insulating film isformed on the polycrystalline silicon film 2 by low pressure CVD througha load locking low pressure CVD apparatus.

[0133] Step 5 (see FIG. 5): An amorphous silicon film 4 a of 2000 Å inthickness is deposited on the gate insulating film 3 by low pressureCVD. This amorphous silicon film 4 a is doped with an impurity (arsenicor phosphorus serving as an N-type impurity, or boron serving as aP-type impurity) in formation thereof. Alternatively, the film 4 a maybe deposited in a non-doped state, so that the impurity is thereafterimplanted into the same.

[0134] Then, a tungsten silicide (WSi_(x)) film 6 b of 1000 Å inthickness is formed on the amorphous silicon film 4 a by sputtering. Inthe sputtering an alloy target of W silicide is employed. While thestoichiometric composition of W silicide (WSi_(x)) is X=2, thecomposition of the alloy target is set at X>2. If the composition of theW silicide film 4 b is close to X=2, extremely high tensile stress takesplace in a later treatment step and the W silicide film 4 b may becracked or separated. However, the resistance value of W silicide isminimized in case of X=2, and hence the upper limit of X must be set tocause neither cracking nor separation.

[0135] A silicon oxide film 5 is deposited on the W silicide film 4 b bynormal pressure CVD, and thereafter the polycrystalline silicon film 4a, the W silicide film 4 b and the silicon oxide film 5 are worked intoprescribed shapes by photolithography and dry etching by RIE. Theamorphous silicon film 4 a is employed as a gate electrode 4 of apolycide structure, along with the W silicide film 4 b.

[0136] Step 6 (see FIG. 6): An impurity is implanted into thepolycrystalline silicon film 2 by self alignment through the gateelectrode 4 and the silicon oxide film 5 serving as masks, therebyforming source/drain regions 6.

[0137] Step 7 (see FIG. 7): A silicon oxide film is deposited on thegate insulating film 3 and the silicon oxide film 5 by normal pressureCVD and anisotropically etched back overall, thereby forming side walls7 on side portions of the gate electrode 4 and the silicon oxide film 5.Further, the side walls 7 and the silicon oxide film 5 are covered witha resist film 8, and an impurity is implanted into the polycrystallinesilicon film 2 again by self alignment through the resist film 8 servingas a mask, thereby forming an LDD (lightly doped drain) structure.

[0138] Step 8 (see FIG. 8): In this state, rapid heating is performed byRTA (rapid thermal annealing).

[0139] Referring to FIG. 30, numeral 105 denotes a heat source foremitting sheet-type annealing light, which is formed by verticallyopposing a pair of xenon (Xe) arc lamps 106 and a pair of reflectingmirrors 107 covering the same to each other. Numeral 108 denotes rollersfor carrying a substrate 1, numeral 109 denotes a preheater forpreheating, and numeral 110 denotes an auxiliary heater for preventingthe heated substrate 1 from being cracked by abrupt cooling.

[0140] In such a structure, the substrate 1 is preheated by thepreheater 109, and thereafter heat treated through the sheet typeannealing light source 105.

[0141] The RTA conditions for this operation are a heat source of an Xearc lamp, a temperature of 700 to 950° C. (pyrometer indicated value),an N₂ atmosphere, and a time of 1 to 3 seconds. Although the heating byRTA is performed at a high temperature, this step can be completed in anextremely short time and hence the substrate 1 is not deformed.

[0142] In order to avoid abrupt application of a high temperature to thesubstrate 1, RTA may be performed a plurality of times. In this case,RTA is performed for 1 to 3 seconds every time, and the temperature isincreased stepwise from 400° C. for the initial time to 700 to 950° C.for the final time.

[0143] The light heat from the Xe arc lamp is more strongly absorbed inan amorphous part and a silicide part as compared with a polycrystallinepart, and hence only necessary portions can be selectively heated. Thus,this step is suitable for reducing the resistance of a (gate) wire andactivating the impurity.

[0144] Due to the rapid heating, the impurity in the source/drainregions 6 is activated and the amorphous silicon film 4 a ispolycrystallized, while the sheet resistance of the gate electrode 4 ina polycide structure by the polycrystalline silicon film 4 a and the Wsilicide film 4 b is reduced to about 20 to 22 Ω/□.

[0145] Further, the sheet resistance of the activated source/drainregions 6 is also reduced to 1 to 1.5 kΩ/□ in case of an N type or 1 to1.2 kΩ/□ in case of a P type, equivalently to a high temperature heattreatment by a diffusion furnace employed in a high temperature process.

[0146] A thin film transistor (TFT) A is formed through this step.

[0147] Step 9 (see FIG. 9): The resist film 8 is removed, and thereafteran interlayer insulating film 9 consisting of a layered structure of aplasma oxide film of 2000 Å in thickness and a silicon oxide film of2000 Å formed by normal CVD is formed on the overall surface of thedevice. If the interlayer insulating film 9 is formed only by thesilicon oxide film by normal CVD, the deposition thickness may be soinhomogeneous that overhangs are formed and Al etc. employed in a laterstep is not removed but tends to remain to cause imperfect insulation.When the silicon oxide film is deposited under the normal pressure afterdeposition of the plasma oxide film according to this embodiment, on theother hand, the growth rate of the silicon oxide film is stabilized andits deposition thickness is homogenous.

[0148] In particular, the plasma oxide film is deposited in ahomogeneous thickness along the irregularity of the substrate surface,whereby the total thickness of the interlayer insulating film 9 ishomogeneously stabilized.

[0149] The deposition conditions for the plasma oxide film are adeposition temperature of 390° C., an RF output of 500 W, an SiH₄ flowrate of 500 sccm, an oxygen flow rate of 1500 sccm and a pressure of 9Torr, and those for the silicon oxide film deposition by normal pressureCVD are a deposition temperature of 400° C., and a carrier N₂ gas flowrate of 3000 cc.

[0150] Then, the device is heated in a hydrogen (H₂) atmosphere at atemperature of 450° C. for 12 hours, and further subjected to a hydrogenplasma treatment. Due to such hydrogenation, hydrogen atoms are bondedto crystal defect portions of the polycrystalline silicon film so thatthe crystal structure is stabilized and field effect mobility isimproved.

[0151] Thereafter contact holes 10 are formed in the interlayerinsulating film 9 by photolithography and dry etching by RIE, to be incontact with the source/drain regions 6.

[0152] Step 10 (see FIG. 10): A wiring layer consisting of a layeredstructure of Ti/Al-Si alloy/Ti is deposited by magnetron sputtering, andworked into source/drain electrodes 11 by photolithography and dryetching by RIE.

[0153] Step 11 (see FIG. 11): A silicon oxide film (or a silicon nitridefilm) 12 for serving as a protective layer is thinly deposited on theoverall surface of the device by CVD.

[0154] Step 12 (see FIG. 12): An SOG (spin on glass) film 13 is appliedonto the overall surface of the device three times, for flattening theirregular surface of the device.

[0155] Step 13 (see FIG. 13): Since the SOG film 13 has inferior resistseparability and tends to absorb moisture, a silicon oxide film (or asilicon nitride film) 14 is further thinly deposited on the SOG film 13by CVD, for serving as a protective layer.

[0156] Step 14 (see FIG. 14): A contact hole 15 communicating with thesource/drain electrodes 11 is formed in the silicon oxide film 12, theSOG film 13 and the silicon oxide film 14 by photolithography and dryetching by RIE, and an ITO (indium tin oxide) film 16 for serving as apixel electrode is deposited on the overall surface of the device bysputtering.

[0157] Step 15 (see FIG. 15): In order to finally work the ITO film 16into an electrode shape, a resist pattern is formed on the ITO film 16,which in turn is etched by RIE employing hydrogen bromide gas (HBr), andthe gas is switched to chlorine gas (Cl₂) when exposure of the siliconoxide film 14 is started, for continuously performing the etching to thelast as such.

[0158] Step 16 (see FIG. 16): After one TFT substrate of an LCD isformed in the aforementioned manner, a transparent insulating substrate18 which is provided with a common electrode 17 on its surface isopposed thereto and a liquid crystal layer 19 is formed by sealingliquid crystals between the substrates 1 and 18, thereby completing apixel part 20 of the LCD.

[0159]FIG. 17 is a block diagram showing an active matrix LCD in thisembodiment.

[0160] Scanning lines (gate wires) G1 . . . Gn, Gn+1 . . . Gm and datalines (drain wires) D1 . . . Dn, Dn+1 . . . Dm are arranged on the pixelpart 20. The gate wires and the drain wires intersect with each other,so that pixels 21 are provided on the intersections. The gate wires areconnected to a gate driver 22, so that gate signals (scan signals) areapplied thereto. On the other hand, the drain wires are connected to adrain driver (data driver) 23, so that data signals (video signals) areapplied thereto. These drivers 22 and 23 form a peripheral drivingcircuit 24.

[0161] An LCD prepared by forming at least one of the drivers 22 and 23on the same substrate as the pixel part 20 is generally called adriver-integrated LCD (LCD having built-in drivers). In this LCD, thegate driver 22 or the drain driver 23 may be provided on each end of thepixel part 20.

[0162] A polycrystalline silicon TFT which is prepared in a similarmanner to the polycrystalline silicon TFT (A) is employed also as eachswitching element of the peripheral driving circuit 24, and this TFT isformed on the same substrate in parallel with preparation of thepolycrystalline TFT (A). The polycrystalline silicon TFT for theperipheral driving circuit 24 is not in an LDD structure, but in ageneral single drain structure. However, this polycrystalline siliconTFT may alternatively have the LDD structure, as a matter of course.

[0163] The polycrystalline silicon TFT of the peripheral driving circuit24 is formed in a CMOS structure, thereby implementing dimensionalreduction of the drivers 22 and 23.

[0164]FIG. 18 illustrates an equivalent circuit of the pixel 21 providedon the intersection between the gate wire Gn and the drain wire Dn.

[0165] The pixel 21 is formed by a TFT, which is similar to the thinfilm transistor A, for serving as a pixel driving element, a liquidcrystal cell LC, and a storage capacitance Cs. The gate and the drain ofthe TFT are connected to the gate wire Gn and the drain wire Dnrespectively. Further, a display electrode (pixel electrode) of theliquid cell LC and the storage capacitance (additional capacitance) Csare connected to the source of the TFT.

[0166] A signal storage element is formed by the liquid crystal cell LCand the storage capacitance Cs. A voltage Vcom is applied to a commonelectrode, which is opposite to the display electrode, of the liquidcrystal cell LC. On the other hand, a constant voltage VR is applied toan electrode of the storage capacitance Cs which is opposite to the sideconnected with the source of the TFT. The common electrode of the liquidcrystal cell LC is literally common to all pixels 21. An electrostaticcapacitance is formed between the display electrode and the commonelectrode of the liquid crystal cell LC. In the storage capacitance Cs,the electrode opposite to the side connected with the source of the TFTmay be connected with the adjacent gate wire Gn+1.

[0167] When the gate wire Gn is set at a positive voltage and thepositive voltage is applied to the gate of the TFT in the pixel 21having the aforementioned structure, the TFT is turned on. Then, theelectrostatic capacitance of the liquid crystal cell LC and the storagecapacitance Cs are charged with the data signal which is applied to thedrain wire Dn. When the gate wire Gn is set at a negative voltage andthe negative voltage is applied to the gate of the TFT, on the otherhand, the TFT is turned off so that the voltage currently applied to thedrain wire Dn is held by the electrostatic capacitance of the liquidcrystal cell LC and the storage capacitance Cs. Thus, it is possible tomake the pixel 21 hold an arbitrary data signal by supplying a datasignal to be written in the pixel 21 to the drain wire and controllingthe voltage of the gate wire. The transmittance of the liquid crystalcell LC is varied with the data signal held by the pixel 21, therebydisplaying a picture.

[0168] Important characteristics of the pixel 21 are writability andholdability. Required for the writability is the point whether or not adesired video signal voltage can be sufficiently written in the signalstorage element (the liquid crystal cell LC and the storage capacitanceCs) in a unit time which is set in relation to the specification of thepixel part 20. On the other hand, required for the holdability is thepoint whether or not the video signal voltage once written in the signalstorage element can be held by a necessary time.

[0169] The storage capacitance Cs is adapted to increase theelectrostatic capacitance of the signal storage element therebyimproving the writability and the holdability. The liquid crystal cellLC is limited in increase of the electrostatic capacitance, due to itsstructure. Thus, the storage capacitance Cs is adapted to compensate forthe insufficient electrostatic capacitance of the liquid crystal cellLC.

[0170] A second embodiment according to the first aspect of the presentinvention is now described with reference to FIGS. 19 to 28. Portionsequivalent to those described with reference to the first embodiment aredenoted by the same reference numerals, to omit redundant description.In the second embodiment, steps corresponding to the steps 1 to 8 of thefirst embodiment are different, and hence only these steps aredescribed.

[0171] Step (1) (see FIG. 19): A W silicide film 41 is formed on asubstrate 1.

[0172] Step (2) (see FIG. 20): The W silicide film 41 is worked into thesame pattern as a polycrystalline silicon film serving as an activelayer of a transistor.

[0173] Step (3) (see FIG. 21): An insulating thin film 1 a of SiO₂ orSiN is formed by CVD or sputtering, to cover the substrate 1 and the Wsilicide film 41.

[0174] Step (4) (see FIG. 22): An amorphous silicon film 2 a is formedon the insulating thin film 1 a.

[0175] Step (5) (see FIG. 23): The surface of the amorphous silicon film2 a is scanned with a KrF excimer laser beam to be annealed, melted andrecrystallized for forming a polycrystalline silicon thin film 2.

[0176] The KrF excimer laser beam may be replaced with an XeCl excimerlaser beam or an ArF excimer laser beam.

[0177] Step (6) (see FIG. 24): The polycrystalline silicon film 2 isworked into a prescribed shape by photolithography and dry etching byRIE, to be employed as an active layer of a thin film transistor.

[0178] Then, an LTO film 3 for serving as a gate insulating film isformed on the polycrystalline silicon film 2.

[0179] Step (7) (see FIG. 25): An amorphous silicon film 4 a isdeposited on the gate insulating film 3.

[0180] Then, a W silicide film 4 b is formed on the amorphous siliconfilm 4 a.

[0181] A silicon oxide film 5 is deposited on the W silicide film 4 b,and thereafter the polycrystalline silicon film 4 a, the W silicide film4 b and the silicon oxide film 5 are worked into prescribed shapes byphotolithography and dry etching by RIE. The amorphous silicon film 4 ais employed as a gate electrode 4 of a polycide structure, along withthe W silicide film 4 b.

[0182] Step (8) (see FIG. 26): A silicon oxide film is deposited on thegate insulating film 3 and the silicon oxide film 5 by normal pressureCVD, and anisotropically etched back overall, thereby forming side walls7 on side portions of the gate electrode 4 and the silicon oxide film 5.

[0183] Then, phosphorus (P) ions are implanted as an impurity by selfalignment through the side walls 7 serving as masks, under conditions ofan acceleration voltage of 80 KeV and a dosage of 3×10¹³ cm⁻², forforming low concentration impurity regions 6 a.

[0184] Step (9) (see FIG. 27): The side walls 7 and the silicon oxidefilm 5 are covered with a resist film 8, and phosphorus (P) ions areimplanted as an impurity by self alignment again through the resist film8 serving as a mask under conditions of an acceleration voltage of 80KeV and a dosage of 1×10¹⁵ cm⁻² for forming high concentration impurityregions 6 b, thereby forming source/drain regions 6 of an LDD (lightlydoped drain) structure.

[0185] Step (10) (see FIG. 28): In this state, rapid heating isperformed by RTA, similarly to the first embodiment.

[0186] Light heat from an Xe arc lamp is more strongly absorbed in anamorphous part and a silicide part as compared with a polycrystallinepart, and hence only necessary portions can be selectively heated. Thus,this step is suitable for reducing the resistance of a (gate) wire andactivating the impurity.

[0187] Particularly in this embodiment, the W silicide film 41 is formedin correspondence under the polycrystalline silicon film 2. This Wsilicide film 41 has a function of absorbing the heat in RTA, and theimpurity contained in the polycrystalline silicon film 2 is activatedalso by radiation heat from the W silicide film 41 absorbing heat.Namely, the polycrystalline silicon film 2 is directly and indirectlyheated by the heat from the Xe arc lamp and the radiation heat from theW silicide film 41, so that the overall polycrystalline silicon film 2is homogeneously heated and the activation is excellently performed withno dispersion.

[0188] The size of the W silicide film 41 may be basically identical toor larger than that of the polycrystalline silicon film 2, while the Wsilicide film 41 is more preferably adjusted to have an areacorresponding to the size of an in-plane pattern.

[0189] In an integrated semiconductor device, pattern irregularity iscaused on its substrate. If W silicide films 2 are equally provided onrespective transistors, therefore, thermal absorptivity per unit area isvaried with the position and the heat treatment cannot be homogeneouslyperformed, while the temperature may be extremely increased in a portionwhere the W silicide films 41 are concentrated, to deform the substrate1.

[0190] When the density per unit area of heat absorption films arrangedas lower layers is rendered substantially constant regardless ofpatterns formed on upper layers, therefore, it is possible to eliminatedisplacement in temperature distribution in activation by RTA. In theconcrete, the pixel part of a driver-integrated LCD panel has a highertransistor density than the driver part, and hence the temperaturedistribution of the overall substrate 1 can be substantially homogenizedby increasing the size of each W silicide film 41 corresponding to eachtransistor of the driver part as compared with that in the pixel part.

[0191] The LCD panel is preferably so adjusted that about 10% of thecircuit area is occupied by W silicide films 41.

[0192] Through this step, a polycrystalline silicon TFT (thin filmtransistor) A is formed.

[0193] According to this embodiment, the polycrystalline silicon TFT canbe fabricated in the so-called low temperature process, with employmentof a high-quality polycrystalline silicon film as an active layer.

[0194] According to an experiment made by the inventor, it has beenproved possible to implement transistors of high performance withmobility μn of at least 200 cm²/V·s in an n-channel MOS polycrystallinesilicon TFT and mobility μp of at least 150 cm²/V·s in a p-channel MOSpolycrystalline silicon TFT.

[0195] Such a high performance TFT is sufficiently applicable to an LCDpanel for displaying NTSC television signals requiring mobility μn of 50cm²/V·s or μp of 20 cm²/V·s, for example, and can attain characteristicsof mobility μn of 50 cm²/V·s or μp of 20 cm²/V·s, a threshold voltage of2 V (n channel) or −5 V (p channel), an S value (sub-threshold swingvalue) of 0.2 V/decade, and an ON-OFF ratio of 1×10⁷.

[0196] The drivability of the TFT is improved due to the high mobility,whereby the size of the TFT can be reduced to not more than ⅛ (W/L=8/5μm) as compared with a conventional transistor (W/L=34/10 μm) employingan active layer of amorphous silicon. Due to the high-quality activelayer, further, a leakage current is small in an OFF state of thetransistor, and the area of the storage capacitance can be reduced tonot more than ⅓.

[0197] In the concrete, a high numerical aperture of 55% (1.5 times ascompared with the prior art) can be attained in a size 2.4 type panelwith high concentration pixels of at least three times the conventionalpanel at pixel pitches of 50.0 (H) μm by 150 (V) μm and a pixel numberof 2,300,000 dots (320×3 (RGB)×240), thereby implementing improvement inluminance.

[0198] The aforementioned embodiment can be modified as follows, toattain functions and effects similar to the above:

[0199] 1) The substrate 1 can also be formed by an ordinary glass plateor the like, depending on conditions.

[0200] 2) In the step 2 or (4), the amorphous silicon film 2 a isdeposited by low pressure CVD with monosilane gas, for example, at atemperature of 580° C. Thus, the amorphous silicon film 2 a containsmicrocrystals.

[0201] When the amorphous silicon film 2 a containing microcrystals ispolycrystallized by solid-phase crystallization, the crystal growth canbe completed in a short time although the mobility is slightly reduceddue to the reduction of the crystal grain sizes.

[0202] 3) In the step 2 or (4), the amorphous silicon film 2 a is formednot by low pressure CVD or plasma CVD but by any one of a groupconsisting of normal pressure CVD, photoexcitation CVD, vapordeposition, EB (electron beam) deposition, MBE (molecular beam epitaxy),and sputtering.

[0203] 4) A portion of the polycrystalline silicon film 2 correspondingto a channel region is doped with an impurity, for controlling thethreshold voltage (Vth) of the polycrystalline silicon TFT. In apolycrystalline silicon TFT formed by solid-phase crystallization, thethreshold voltage tends to shift in a depression direction in case of anN-channel transistor, or in an enhancement direction in case of aP-channel transistor. This tendency further remarkably appears whenhydrogenation is performed. In order to suppress such shifting of thethreshold voltage, the channel region may be doped with an impurity.

[0204] 5) The step 3 or (5) is replaced with the following step:

[0205] Step 3 a: A heat treatment is performed in an electric furnace ina nitrogen (N₂) atmosphere at a temperature of about 600° C. for about20 hours, thereby forming the polycrystalline silicon film 2 bysolid-phase crystallization of the amorphous silicon film 2 a.

[0206] 6) In the polycrystalline silicon film 2 formed in the step 3 a,a number of defects such as dislocations are present in crystals formingthe film while amorphous parts may remain between the crystals, toresult in a high leakage current.

[0207] After the step 3 a, therefore, the substrate 1 is rapidly heatedby RTA or laser annealing, for improving the film quality of thepolycrystalline silicon film 2.

[0208] 7) The electric furnace can treat a number of substrates at oncealthough the same requires a longer time as compared with laserirradiation, and hence each of the steps 5) and 6) substantially hashigh throughput. Therefore, the subsequent heat treatment for activatingthe impurity regions, for example, may be performed by laser beamannealing, in place of RTA. The RTA has such an advantage that thetreatment can be completed in a short time, while the laser annealinghas such an advantage that sheet resistance can be reduced since thetemperatures of the impurity regions can be increased to high levels.

[0209] 8) In the step 5, (1) or (7), the W silicide film 4 b or 41 isformed by PVD such as vacuum deposition, ion plating, ion beamdeposition, a cluster ion beam method or the like, in place ofsputtering. Also in this case, the composition of W silicide (WSi_(x))is set at X>2 for a reason similar to that for the aforementionedsputtering.

[0210] 9) In the step 5, (1) or (7), the W silicide film 4 b or 41 isformed by CVD. The source gas therefor may be prepared from tungstenhexafluoride (WF₆) and silane (SiH₄). The film forming temperature isset at about 350 to 450° C. Also in this case, the composition of Wsilicide (WSi_(x)) is set at X>2 for a reason similar to that for theaforementioned sputtering. The CVD is superior in step coverage to thePVD, whereby the thickness of the W silicide film 4 b can be furtherhomogenized.

[0211] 10) In place of W silicide employed for the gate electrode, highmelting point metal silicide such as MoSi₂, TiSi₂, TaSi₂ or CoSi₂, or ahigh melting point metal such as W, Mo, Co, Cr, Ti or Ta may beemployed.

[0212] 11) In the step 9, the plasma oxide film may be replaced with aplasma TEOS oxide film employing TEOS (tetraethyl orthosilicate ortetraethoxysilane), or the silicon oxide film may be replaced with anormal pressure ozone TEOS oxide film.

[0213] Deposition conditions for the plasma TEOS oxide film are adeposition temperature of 390° C., an RF output of 500 W, a TEOS flowrate of 500 sccm, an oxygen flow rate of 600 sccm and a pressure of 9Torr, and those for the normal pressure ozone TEOS oxide film are adeposition temperature of 400° C., an RF output of 300W, ozoneconcentration of about 5 wt. %, and a TEOS carrier N₂ gas flow rate of3000 cc.

[0214] 12) When the plasma TEOS oxide film is exposed to nitrogen ionsby a plasma treatment with ammonia (NH₃) gas after the step 11) so thatits surface is nitrided and thereafter a normal pressure ozone TEOSoxide film is deposited, the growth rate of the silicon oxide film isfurther stabilized. The nitriding conditions are a temperature of 360°C., an RF output of 500 W, an ammonia flow rate of 100 to 500 sccm, andan N₂ flow rate of 0 to 400 sccm. In this nitriding, ammonia may bereplaced with nitrogen.

[0215] 13) In place of the W silicide film 41, a semiconductor film suchas an amorphous silicon film or a polycrystalline silicon film isemployed. Such a silicon film may be doped with an impurity. When aconductive or semiconductor film is employed and a voltage is applied tothis heat absorption film, the TFT can be driven as a four-terminaldevice similarly to a MOS transistor which is applied to an LSI forcontrolling the threshold voltage. When a glass substrate is employed,on the other hand, the transistor can be electrostatically shieldedagainst ions contained in the substrate, and prevented fromdeterioration of the characteristics caused by the ions in the glasssubstrate and from a bad influence exerted by potentials formed bymovable ions.

[0216] 14) In place of the W silicide film 41, a film of high meltingpoint metal silicide such as MoSi₂, TiSi₂, TaSi₂ or CoSi₂, or a highmelting point metal such as W, Mo, Co, Cr, Ti or Ta may be employed.When the employed temperature is low (not more than about 450° C.), theso-called low melting point metal such as Al or Au may be employed.

[0217] Such a metal film (including the W silicide film) has a propertyof transmitting no light, whereby the following effects are attained:

[0218] a) The film prevents scattering of light and shields the liquidcrystal cell against unnecessary light obliquely entering the same,whereby the contrast of the LCD device is improved.

[0219] b) The film shields the TFT against light entering the same,whereby a leakage current caused by the light is reduced for improvingthe characteristics of the TFT, while deterioration of the TFT itselfcaused by the light is prevented.

[0220] 15) The present invention is applied to not only to a planar typeTFT but polycrystalline silicon TFTs of all structures such asreverse-planar, stagger and reverse-stagger type TFTs.

[0221] 16) The present invention is applied not only to apolycrystalline silicon TFT but to general insulated gate semiconductordevices. Further, the present invention is applied to all semiconductordevices employing polycrystalline silicon films such as photoelectricconversion elements such as a solar cell and an optical sensor, abipolar transistor, a static induction transistor (SIT) and the like.

[0222] An embodiment according to the second to fifth aspects of thepresent invention is now described with reference to FIGS. 33 to 42.

[0223] Step 1 (see FIG. 33): A tungsten silicide (WSi_(x)) film 62 of1000 Å in thickness, which is adjustable in the range of 50 to 2000 Å,is formed on a substrate 61 of quartz glass or no-alkali glass bysputtering. In the sputtering, an alloy target of W silicide isemployed. While the stoichiometric composition of W silicide (WSi_(x))is X=2, the composition of the alloy target is set at X>2. If thecomposition of the W silicide film 62 is close to X=2, extremely hightensile stress takes place in a later treatment step and the W silicidefilm 62 may be cracked or separated. However, the resistance value ofthe W silicide is minimized in case of X=2, and hence the upper limit ofX must be set to cause neither cracking nor separation.

[0224] Step 2 (see FIG. 34): The W silicide film 62 is worked into thesame pattern as a polycrystalline silicon film for serving as an activelayer of a transistor as described later, by lithography and etching.

[0225] Step 3 (see FIG. 35): An insulating thin film 63 of SiO₂ or SiNis formed by CVD or sputtering, to cover the substrate 61 and the Wsilicide film 62. In the concrete, the substrate 61 is prepared fromno-alkali glass, so that an SiO₂ film of 3000 to 5000 Å in thickness isformed on its surface by normal or low pressure CVD at a formationtemperature of 350° C.

[0226] This SiO₂ film must have such a thickness that no impurity passesthrough the SiO₂ film to diffuse into an upper layer from the substrate61 in a later step of a heat treatment or irradiation with a beam. Thisthickness is properly selected in the range of 1000 to 6000 Å, and anexcellent diffusion preventing effect can be attained when the thicknessis in the range of 2000 to 6000 Å, most properly in the range of 2000 to5000 Å.

[0227] When the insulating thin film 63 is prepared from SiN, on theother hand, the thickness of this film is properly selected in the rangeof 1000 to 5000 Å, and an excellent diffusion preventing effect can beattained when the thickness is in the range of 2000 to 5000 Å, mostproperly in the range of 2000 to 3000 Å.

[0228] Step 4 (see FIG. 36): An amorphous silicon film 64 a of 500 Å inthickness is formed on the insulating thin film 63. When the amorphoussilicon film 64 a is employed as an active layer of a polycrystallineTFT, the OFF-state current of the TFT is increased if the thickness ofthe active layer is too large while the ON-state current is reduced ifthe thickness is too small. Therefore, the thickness of the amorphoussilicon film 64 a is properly selected in the range of 400 to 800 Å, andexcellent characteristics are attained when the thickness is in therange of 500 to 700 Å, most properly in the range of 500 to 600 Å.

[0229] The amorphous silicon film 64 a is formed in the followingmanner:

[0230] (1) With employment of low pressure CVD: In order to form theamorphous silicon film 64 a by low pressure CVD, thermal decompositionof monosilane (SiH₄) or disilane (Si₂H₆) is employed. When monosilane isemployed, the film becomes amorphous when the treatment temperature isnot more than 550° C., or becomes polycrystalline when the treatmenttemperature is in excess of 620° C. In the treatment temperature rangeof 550 to 620° C., the ratio of amorphous materials includingmicrocrystals is increased, and the film approaches an amorphous stateand the ratio of the microcrystals is reduced as the temperature isreduced. Thus, the amount of microcrystals contained in the amorphoussilicon film 64 a can be adjusted by simply changing the temperaturecondition.

[0231] (2) With employment of plasma CVD: In order to form the amorphoussilicon film 64 a by plasma CVD, thermal decomposition of monosilane ordisilane in a plasma is employed.

[0232] In practice, plasma CVD is employed for forming an amorphoussilicon film containing no microcrystals with monosilane gas under atemperature of 350° C.

[0233] Step 5 (see FIG. 37): The surface of the amorphous silicon film64 a is irradiated and scanned with a KrF excimer laser beam having awavelength λ of 248 nm to be annealed, melted and recrystallized forforming a polycrystalline silicon thin film 64.

[0234] The laser conditions for this step are an annealing atmosphere ofnot more than 1×10⁻⁴ Pa, a substrate temperature in the range of theroom temperature to 600° C., irradiation energy density of 100 to 500mJ/cm², and a scanning rate of 1 to 10 mm/sec. (in practice, the filmcan be scanned at a rate in the range of 0.1 to 100 mm/sec.).

[0235] The KrF laser beam may be replaced with an XeCl excimer laserbeam having a wavelength λ of 308 nm. In this case, the laser conditionsare an annealing atmosphere of not more than 1×10⁻⁴ Pa, a substratetemperature in the range of the room temperature to 600° C., irradiationenergy density of 100 to 500 mJ/cm², and a scanning rate of 1 to 10mm/sec. (in practice, the film can be scanned at a rate in the range of0.1 to 100 mm/sec.).

[0236] Alternatively, an ArF excimer laser beam having a wavelength λ of193 nm may be employed. In this case, the laser conditions are anannealing atmosphere of not more than 1×10⁻⁴ Pa, a substrate temperaturein the range of the room temperature to 600° C., irradiation energydensity of 100 to 500 mJ/cm², and a scanning rate of 1 to 10 mm/sec.

[0237] In any case, the grain size of polycrystalline silicon isincreased in proportion to the irradiation energy density and the numberof irradiation times, and hence the energy density may be adjusted toattain a desired grain size.

[0238] According to this embodiment, the high throughput laserirradiation shown in FIG. 29 is employed for this excimer laserannealing.

[0239] Step 6 (see FIG. 38): The polycrystalline silicon film 64 isworked into a prescribed shape by photolithography and dry etching byRIE, to be employed as an active layer of a thin film transistor.

[0240] Then, an LTO film (low temperature oxide film: silicon oxidefilm) 65 of 1000 Å in thickness for serving as a gate insulating film isformed on the polycrystalline silicon film 64 by low pressure CVDthrough a load locking low pressure CVD apparatus.

[0241] Step 7 (see FIG. 39): An amorphous silicon film 66 a of 2000 Å inthickness is deposited on the gate insulating film 65 by low pressureCVD. This amorphous silicon film 66 a is doped with an impurity (arsenicor phosphorus serving as an N-type impurity, or boron serving as aP-type impurity) in formation thereof. Alternatively, the film 66 a maybe deposited in a non-doped state, so that the impurity is thereafterimplanted into the same.

[0242] Then, a tungsten silicide (WSi_(x)) film 66 b of 1000 Å inthickness is formed on the amorphous silicon film 66 a by sputtering.

[0243] Then, a silicon oxide film 67 is deposited on the W silicide film66 b by normal pressure CVD, and thereafter the polycrystalline siliconfilm 66 a, the W silicide film 66 b and the silicon oxide film 67 areworked into prescribed shapes by photolithography and dry etching byRIE. The amorphous silicon film 66 a is employed as a gate electrode 66of a polycide structure, along with the W silicide film 66 b.

[0244] Step 8 (see FIG. 40): A silicon oxide film is deposited on thegate insulating film 65 and the silicon oxide film 67 by normal pressureCVD and anisotropically etched back overall, thereby forming side walls68 on side portions of the gate electrode 66 and the silicon oxide film67.

[0245] Then, phosphorus (P) ions are implanted into the polycrystallinesilicon film 64 as an impurity by self alignment through the side walls68 serving as masks, under conditions of an acceleration voltage of 80KeV and a dosage of 3×10¹³ cm⁻², for forming low concentration impurityregions 69 a.

[0246] Step 9 (see FIG. 41): The side walls 68 and the silicon oxidefilm 67 are covered with a resist film 70, and phosphorus (P) ions areimplanted into the polycrystalline silicon film 64 as an impurity againby self alignment through the resist film 70 serving as a mask underconditions of an acceleration voltage of 80 KeV and a dosage of 1×10¹⁵cm⁻² for forming high concentration impurity regions 69 b, therebyforming source/drain regions 69 of an LDD (lightly doped drain)structure.

[0247] Step 10 (see FIG. 42): In this state, rapid heating is performedby the RTA (rapid thermal annealing) shown in FIG. 30.

[0248] The RTA conditions for this operation are a heat source of an Xearc lamp, a temperature of 700 to 950° C. (pyrometer), an N₂ atmosphere,and a time of 1 to 3 seconds. Although the heating by RTA is performedat a high temperature, this step can be completed in an extremely shorttime and hence the substrate 61 is not deformed.

[0249] In order to avoid abrupt application of a high temperature to thesubstrate 61, RTA may be performed a plurality of times. In this case,RTA is performed for 1 to 3 seconds every time, and the temperature isincreased stepwise from 400° C. for the initial time to 700 to 950° C.for the final time.

[0250] In more concrete terms, the heating may be performed six times,for example, in a nitrogen (N₂) atmosphere, so that the treatmenttemperature is increased stepwise every time. For example, thetemperature is gradually increased as 400° C. (pyrometer, identical forthe rest) for the initial time (first time)→500° C. for the second time550° C. for the third time→600° C. for the fourth time→650° C. for thefifth time→700° C. for the final time (sixth time). Thus, the substrate61 can be prevented against warp or breakage. The treatment time is 1 to3 seconds every time, for example.

[0251] The temperature can be adjusted by not turning on the Xe arc lamp106 but employing the heat of the preheater 109 at the initial time andchanging the power of the Xe arc lamp 106 in the range of 1 to 7 KW fromthe second time.

[0252] Light heat from the Xe arc lamp is more strongly absorbed in anamorphous part and a silicide part as compared with a polycrystallinepart, and hence only necessary portions can be selectively heated. Thus,this step is suitable for reducing the resistance of a (gate) wire andactivating the impurity. Further, heating through the W silicide film 62can also be effectively performed, as described later.

[0253] Due to the rapid heating, the impurity in the source/drainregions 69 is activated and the amorphous silicon film 66 a ispolycrystallized, while the sheet resistance of the gate electrode 66 ina polycide structure by the polycrystalline silicon film 66 a and the Wsilicide film 66 b is reduced to about 20 to 22 Ω/□.

[0254] Further, the sheet resistance of the activated source/drainregions 66 is also reduced to 1 to 1.5 kΩ/□ in case of an N type or 1 to1.2 kΩ/□ in case of a P type, equivalently to a high temperature heattreatment by a diffusion furnace employed in a high temperature process.

[0255] Particularly in this embodiment, the W silicide film 62 is formedin correspondence under the polycrystalline silicon film 64. This Wsilicide film 62 has a function of absorbing the heat in RTA, and theimpurity contained in the polycrystalline silicon film 64 is activatedalso by radiation heat from the W silicide film 62 absorbing heat.Namely, the polycrystalline silicon film 64 is directly and indirectlyheated by the heat from the Xe arc lamp and the radiation heat from theW silicide film 62, so that the overall polycrystalline silicon film 64is homogeneously heated and the activation is excellently performed withno dispersion.

[0256] The size and region of the W silicide film 62 may besubstantially identical to or smaller than that of the polycrystallinesilicon film 64. The term “substantially” means the range including ±2%.

[0257] In an integrated semiconductor device, pattern irregularity iscaused on its substrate. If W silicide films 62 are equally provided onrespective transistors, therefore, thermal absorptivity per unit area isvaried with the position and the heat treatment cannot be homogeneouslyperformed, while the temperature may be extremely increased in a portionwhere the W silicide films 62 are concentrated, to deform the substrate61.

[0258] When the density per unit area of heat absorption films arrangedas lower layers is rendered substantially constant regardless ofpatterns formed on upper layers, therefore, it is possible to eliminatedisplacement in temperature distribution in activation by RTA. In theconcrete, the pixel part of a driver-integrated LCD panel has a highertransistor density than the driver part, and hence the temperaturedistribution of the overall substrate 61 can be substantiallyhomogenized by increasing the size of each W silicide film 62corresponding to each transistor of the driver part as compared withthat in the pixel part.

[0259] The LCD panel is preferably so adjusted that about 10% of thecircuit area is occupied by W silicide films 62.

[0260] Through this step, a polycrystalline silicon TFT (thin filmtransistor) A is formed.

[0261] The structure of a pixel part of an LCD having a transmissionstructure employing the polycrystalline silicon TFT (A) fabricated inthe aforementioned manner as each pixel driving element with referenceto FIG. 43.

[0262] Step [1]: In advance of formation of an interlayer insulatingfilm 71, a storage electrode 72 of a storage capacitance consisting ofITO (indium tin oxide) is formed on a pixel part region of the substrate61 by sputtering.

[0263] Step [2]: An insulating film 73 is formed on the overall surfaceof the device. The insulating film 73 is made of silicon oxide, silicateglass or silicon nitride, and formed by CVD or PVD.

[0264] Then, contact holes are formed in the insulating film 73 to be incontact with source/drain electrodes 74, an ITO film is formed on theoverall surface of the device including the contact holes, and this ITOfilm is patterned for forming a display electrode 75.

[0265] Step [3]: The transparent insulating substrate 61 provided withthe polycrystalline silicon TFT (A) is opposed to a transparentinsulating substrate 77 provided with a common electrode 76 on itssurface, and liquid crystals are sealed between the substrates 61 and 71for forming a liquid crystal layer 78. Consequently, a pixel part of theLCD is completed.

[0266] The pixel part formed in the aforementioned manner can beemployed as that of the active matrix LCD shown in FIGS. 17 and 18.

[0267] In the aforementioned embodiment, the size and region of the Wsilicide film 62 may be substantially identical to or smaller than thatof the polycrystalline silicon film 64.

[0268]FIG. 44 is a plan view showing the region for providing the Wsilicide film 62 which is the heat absorption film. Referring to FIG.44, the W silicide film 62 is provided in the substantially same region(shown by hatching) as the polycrystalline silicon film 64. In theperipheral driving circuit part, in which the semiconductor films arerelatively concentrated compared to the pixel part, the heat absorptionfilm is preferably provided in a smaller size within the regioncorresponding to the semiconductor film.

[0269]FIG. 45 is a plan view showing another exemplary region of theheat absorption film according to the present invention. Referring toFIG. 45, the heat absorption film 62 is provided only in a channelregion 64 a (shown by hatching) of the polysilicon film.

[0270] In an integrated semiconductor device, pattern irregularity iscaused on its substrate as described above. If W silicide films 62 areequally provided on respective transistors, therefore, thermalabsorption per unit area is varied with the position and the heattreatment cannot be homogeneously performed, while the temperature maybe extremely increased in a portion where the W silicide films 62 areconcentrated, to deform the substrate 61.

[0271] When the density per unit area of the W silicide films 62arranged as lower layers is rendered substantially constant regardlessof patterns formed on upper layers, therefore, it is possible toeliminate displacement in temperature distribution in activation by RTA.

[0272] In a driver-integrated LCD panel such as that of this embodiment,the concentration of the TFTs (A) in the pixel part 20 is higher thanthat in the peripheral driving circuit part 24, and hence thetemperature distribution of the overall substrate 61 is substantiallyhomogenized when the area of each W silicide film 62 corresponding toeach TFT (A) of the peripheral driving circuit part 24 is increasedbeyond that in the pixel part 20. In the LCD panel, the peripheraldriving circuit part 24 requires no transmittance, and hence the sizesof the W silicide films 62 can be adjusted in the range of zero to theoverall region of the peripheral driving circuit part 24.

[0273]FIG. 46 is a plan view for explaining ratios of heat absorptionfilms in a pixel part, a peripheral driving circuit part, and the otherregion on a substrate. As described above, the heat absorption film ispreferably provided uniformly over the whole substrate 61. In the pixelpart 20, the heat absorption film is preferably provided in area of 0.01to 60%, further preferably 10 to 50% of the whole circuit area. In theperipheral driving circuit part 24, the heat absorption film ispreferably provided in area of 0.01 to 60%, further preferably 10 to 50%of the whole circuit area. In the region 25 other than the pixel part 20and the peripheral driving circuit part 24, the heat absorption film ispreferably provided in area of 0.01 to 60%, further preferably 10 to 50%of the whole area.

[0274] In place of changing the areas of the W silicide films 62, thethicknesses may be changed.

[0275] The aforementioned embodiment can be modified as follows, toattain functions and effects similar to the above:

[0276] 1) In place of the W silicide film 62, a semiconductor film suchas an amorphous silicon film or a polycrystalline silicon film isemployed. Such a silicon film may be doped with an impurity. When aconductive or semiconductor film is employed and a voltage is applied tothis heat absorption film, the TFT can be driven as a four-terminaldevice similarly to a MOS transistor which is applied to an LSI forcontrolling the threshold voltage. When a glass substrate is employed,on the other hand, the transistor can be electrostatically shieldedagainst ions which are present in the substrate, and prevented againstdeterioration of characteristics caused by the ions in the glasssubstrate and from a bad influence exerted by potentials formed bymovable ions.

[0277] 2) In place of the W silicide film 62, a film of high meltingpoint metal silicide such as MoSi₂, TiSi₂, TaSi₂ or CoSi₂, or a highmelting point metal such as W, Mo, Co, Cr, Ti or Ta may be employed.When the employed temperature is low (not more than about 450° C.), theso-called low melting point metal such as Al or Au may be employed.

[0278] Such a metal film (including the W silicide film) has a propertyof transmitting no light, whereby the following effects are attained:

[0279] a) The film prevents scattering of light and shields the liquidcrystal cell against unnecessary light obliquely entering the same,whereby the contrast of the LCD device is improved.

[0280] b) The film shields the TFT against light entering the same,whereby a leakage current caused by the light is reduced for improvingthe characteristics of the TFT, while deterioration of the TFT itselfcaused by the light is prevented.

[0281] 3) In the step 4, the amorphous silicon film 64 a is deposited bylow pressure CVD with monosilane gas, for example, at a temperature of580° C. Thus, the amorphous silicon film 64 a contains microcrystals.

[0282] When an amorphous silicon film containing microcrystals ispolycrystallized by solid-phase crystallization, the crystal growth canbe completed in a short time although the mobility is slightly reduceddue to the reduction of the crystal grain sizes.

[0283] 4) In the step 4, the amorphous silicon film is formed not by lowpressure CVD or plasma CVD but by any one of a group consisting ofnormal pressure CVD, photoexcitation CVD, vapor deposition, EB (electronbeam) deposition, MBE (molecular beam epitaxy), and sputtering.

[0284] 5) A portion of the polycrystalline silicon film 64 correspondingto a channel region is doped with an impurity, for controlling thethreshold voltage (Vth) of the polycrystalline silicon TFT. In apolycrystalline silicon TFT formed by solid-phase crystallization, thethreshold voltage tends to shift in a depression direction in case of anN-channel transistor, or in an enhancement direction in case of aP-channel transistor. This tendency further remarkably appears whenhydrogenation is performed. In order to suppress such shifting of thethreshold voltage, the channel region may be doped with an impurity.

[0285] 6) The step 5 is replaced with the following step:

[0286] Step 5 a: A heat treatment is performed in an electric furnace ina nitrogen (N₂) atmosphere at a temperature of about 600° C. for about20 hours, thereby forming the polycrystalline silicon film 64 bysolid-phase crystallization of the amorphous silicon film 64 a.

[0287] 7) In the polycrystalline silicon film 64 formed in the step 5 a,a number of defects such as dislocations are present in crystals formingthe film while amorphous parts may remain between the crystals, toresult in a high leakage current.

[0288] After the step 5 a, therefore, the substrate 61 is rapidly heatedby RTA or laser annealing, for improving the film quality of thepolycrystalline silicon film 64.

[0289] 8) In the step 1 or 7, the W silicide film 62 or 66 b is formedby PVD such as vacuum deposition, ion plating, ion beam deposition, acluster ion beam method or the like, in place of sputtering. Also inthis case, the composition of W silicide (WSi_(x)) is set at X>2 for areason similar to that for the aforementioned sputtering.

[0290] 9) In the step 1 or 7, the W silicide film 62 or 66 b is formedby CVD. The source gas therefor may be prepared from tungstenhexafluoride (WF₆) and silane (SiH₄). The film forming temperature isset at about 350 to 450° C. Also in this case, the composition of Wsilicide (WSi_(x)) is set at X>2 for a reason similar to that for theaforementioned sputtering. The CVD is superior in step coverage to thePVD, whereby the thickness of the W silicide film can be furtherhomogenized.

[0291] 10) The present invention is applied to not only to a planar typeTFT but polycrystalline silicon TFTs of all structures such asreverse-planar, stagger and reverse-stagger type TFTs.

[0292] 11) The present invention is applied not only to apolycrystalline silicon TFT but to general insulated gate semiconductordevices. Further, the present invention is applied to all semiconductordevices employing polycrystalline silicon films such as photoelectricconversion elements such as a solar cell and an optical sensor, abipolar transistor, a static induction transistor (SIT) and the like.

[0293] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A method of fabricating a thin film transistor,comprising the steps of: forming an amorphous silicon film on aninsulating substrate; heat treating said amorphous silicon film by laserannealing or RTA (rapid thermal annealing) employing a temperature notdeforming said substrate, thereby forming a polycrystalline siliconfilm; forming a gate electrode on said polycrystalline silicon filmthrough a gate insulating film; forming an impurity region in saidpolycrystalline silicon film; and heat treating said impurity region bylaser annealing or RTA employing a temperature not deforming saidsubstrate, thereby activating said impurity region; a heat treatmentmethod in said step for forming said polycrystalline silicon film beingdifferent from that in said step for activating said impurity region. 2.The method of fabricating a thin film transistor in accordance withclaim 1 , wherein said amorphous silicon film contains microcrystals. 3.A method of fabricating a thin film transistor having a gate electrodecomprising at least two-layer structure of a silicon film and a metal ormetal silicide film, simultaneously performing reduction of resistanceof said gate electrode and activation of said impurity region by RTA orlaser annealing.
 4. The method of fabricating a thin film transistor inaccordance with claim 1 , wherein light irradiation heat from a xenonarc lamp is employed as a heat source for said RTA.
 5. The method offabricating a thin film transistor in accordance with claim 1 , whereinheating by said RTA is performed a plurality of times while the heatingtemperature is increased stepwise from the initial time to the finaltime.
 6. A liquid crystal display employing thin film transistors beingfabricated by the method in accordance with claim 1 as at least oneelement of each pixel driving element and each peripheral drivingcircuit element.
 7. A semiconductor device comprising: a heat absorptionfilm being formed on a substrate; a semiconductor film being formed onsaid heat absorption film; a gate electrode being formed on saidsemiconductor film through a gate insulating film; and an impurityregion being formed in said semiconductor film; said heat absorptionfilm being provided within a region substantially corresponding to saidsemiconductor film.
 8. The semiconductor device in accordance with claim7 , wherein an insulating film is formed between said heat absorptionfilm and said semiconductor film.
 9. The semiconductor device inaccordance with claim 7 , wherein said heat absorption film is providedin a size and within a region substantially corresponding to a channelregion in said semiconductor film.
 10. The semiconductor device inaccordance with claim 7 , wherein said heat absorption film is made of aconductive material such as a metal or metal silicide, or asemiconductor material such as silicon.
 11. The semiconductor device inaccordance with claim 7 , wherein said heat absorption film has ashading property.
 12. The semiconductor device in accordance with claim7 , wherein said substrate is a transparent substrate.
 13. A displaydevice employing the semiconductor device in accordance with claim 7 asat least one of each pixel driving element and each peripheral drivingcircuit element.
 14. A method of fabricating a semiconductor device byproviding a semiconductor film for serving as an active layer of atransistor on a substrate through a heat absorption film and activatingan impurity region being provided in said semiconductor film by a heattreatment.
 15. A method of fabricating a semiconductor device,comprising the steps of: forming a heat absorption film on a substrate;forming a semiconductor film on said heat absorption film; forming agate electrode on said semiconductor film through a gate insulatingfilm; forming an impurity region in said semiconductor film; andactivating said impurity region by a heat treatment; said heatabsorption film being provided within a region substantiallycorresponding to said semiconductor film.
 16. a method of fabricating asemiconductor device, comprising the steps of: forming a heat absorptionfilm on a substrate; patterning said heat absorption film into aprescribed shape; covering said heat absorption film with an insulatingfilm; forming a semiconductor film for serving as an active layer of atransistor on said insulating film; forming a gate electrode on saidsemiconductor film through a gate insulating film; forming an impurityregion in said semiconductor film; and activating said impurity regionby a heat treatment; said heat absorption film being provided within aregion substantially corresponding to said semiconductor film.
 17. Themethod of fabricating a semiconductor device in accordance with claim 15, wherein said semiconductor film is prepared by polycrystallizing anamorphous silicon film by a heat treatment.
 18. The method offabricating a semiconductor device in accordance with claim 17 , whereinsaid heat treatment is performed by laser annealing.
 19. The method offabricating a semiconductor device in accordance with claim 15 , whereinsaid heat absorption film is made of a conductive material such as ametal or metal silicide, or a semiconductor material such as silicon.20. The method of fabricating a semiconductor device in accordance withclaim 15 , wherein said heat absorption film has a shading property. 21.The method of fabricating a semiconductor device in accordance withclaim 15 , wherein RTA is employed as said heat treatment.
 22. Themethod of fabricating a semiconductor device in accordance with claim 21, wherein a xenon arc lamp is employed as a heat source for said RTA.23. A method of fabricating a display device by employing asemiconductor device being fabricated by the method in accordance withclaim 15 as at least one of each pixel driving element and eachperipheral driving circuit element.
 24. A semiconductor device beingformed by integrating a plurality of semiconductor elements on asubstrate, wherein each said semiconductor element has a heat absorptionfilm provided between said substrate and said semiconductor elements,and an area or film thickness of said heat absorption film is relativelyreduced in a portion where a relatively large number of saidsemiconductor elements are provided, while an area or film thickness ofsaid heat absorption film is relatively increased in a portion where arelatively small number of said semiconductor elements are provided, inaccordance with the distributed state of said semiconductor elements onsaid substrate.
 25. A semiconductor device being formed by integrating aplurality of semiconductor switching elements on a substrate, each saidsemiconductor switching element comprising: a heat absorption film beingformed on said substrate; a semiconductor film being formed on said heatabsorption film; a gate electrode being formed on said semiconductorfilm through a gate insulating film; and an impurity region being formedin said semiconductor film; wherein an area or film thickness of saidheat absorption film is relatively reduced in a portion where arelatively large number of said semiconductor elements are provided,while an area or film thickness of said heat absorption film isrelatively increased in a portion where a relatively small number ofsaid semiconductor elements are provided, in accordance with thedistributed state of said semiconductor elements on said substrate. 26.The semiconductor device in accordance with claim 24 , wherein said areaor film thickness of said heat absorption film is so adjusted that heatabsorption of said absorption film functions substantially uniformly onsaid whole substrate.
 27. The semiconductor device in accordance withclaim 24 , wherein said heat absorption film is made of a conductivematerial such as a metal or metal silicide, or a semiconductor materialsuch as silicon.
 28. A semiconductor device being formed by integratinga plurality of semiconductor elements on a substrate, said plurality ofsemiconductor elements comprising a plurality of first semiconductorelements each having a heat absorption film and a plurality of secondsemiconductor elements each not having a heat absorption film; whereinsaid second semiconductor elements are relatively concentrated in aportion where a relatively large number of said semiconductor elementsare provided, while said first semiconductor elements are relativelyconcentrated in a portion where a relatively small number of saidsemiconductor elements are provided, in accordance with the distributedstate of said semiconductor elements on said substrate.
 29. Adriver-integrated display device having a pixel part and a peripheraldriving circuit part being formed on the same substrate, saiddriver-integrated display device comprising: a pixel driving elementbeing provided in said pixel part; and a peripheral driving circuitelement being provided in said peripheral driving circuit part; whereinsaid pixel driving element and said peripheral driving circuit elementare formed by semiconductor switching elements, and each saidsemiconductor switching element comprises: a heat absorption film beingformed on said substrate, a semiconductor film being formed on said heatabsorption film, a gate electrode being formed on said semiconductorfilm through a gate insulating film, and an impurity region being formedin said semiconductor film, a ratio of area or film thickness of saidheat absorption film relative to said semiconductor film in said pixelpart being adjusted to be larger than that of said heat absorption filmin said peripheral driving circuit part.
 30. The display device inaccordance with claim 29 , wherein said area of said heat absorptionfilm in said pixel part is set to 0.01 to 60% of the whole area of saidpixel part.
 31. The display device in accordance with claim 29 , whereinsaid area of said heat absorption film in said peripheral drivingcircuit part is set to 0.01 to 60% of the whole area of said peripheraldriving circuit part.
 32. The display device in accordance with claim 29, wherein said area of said heat absorption film in said substrate isset to 0.01 to 60% of the whole area of said substrate.
 33. The displaydevice in accordance with claim 29 , wherein said substrate is one of apair of substrates being opposed to each other through a liquid crystallayer.
 34. The display device in accordance with claim 29 , wherein eachsaid heat absorption film is provided in a size and within an areasubstantially corresponding to a channel region of each saidsemiconductor film.
 35. The display device in accordance with claim 29 ,wherein said heat absorption effect of each said heat absorption film isadjusted by changing the area or the thickness of said heat absorptionfilm.
 36. The display device in accordance with claim 29 , wherein aninsulating film is formed on each said heat absorption film.
 37. Thedisplay device in accordance with claim 29 , wherein each said heatabsorption film is made of a conductive material such as a metal ormetal silicide, or a semiconductor material such as silicon.
 38. Thedisplay device in accordance with claim 29 , wherein each said heatabsorption film has a shading property.
 39. The display device inaccordance with claim 29 , wherein said substrate is a transparentsubstrate.
 40. The display device in accordance with claim 29 , whereinRTA employing a xenon arc lamp as a heat source is employed as said heattreatment.
 41. A display device being formed by integrating a pluralityof semiconductor elements on a substrate, said plurality ofsemiconductor elements comprising a plurality of first semiconductorelements each having a heat absorption film and a plurality of secondsemiconductor elements each not having a heat absorption film; whereinsaid second semiconductor elements are relatively concentrated in aportion where a relatively large number of said semiconductor elementsare provided, while said first semiconductor elements are relativelyconcentrated in a portion where a relatively small number of saidsemiconductor elements are provided, in accordance with the distributedstate of said semiconductor elements on said substrate.
 42. A method offabricating a semiconductor device, comprising the steps of: forming asemiconductor film on a substrate; forming a gate electrode on saidsemiconductor device through a gate insulating film; forming an impurityregion in said semiconductor film; and activating said impurity regionby a heat treatment through RTA, heating by said RTA being performed aplurality of times, the heating temperature being increased stepwisefrom the initial time to the final time.
 43. The method of fabricating asemiconductor device in accordance with claim 42 , wherein the highestheating temperature in said stepwise increasing in temperature throughRTA is a temperature not deforming said substrate.